Design for Test (DFT) techniques are widely known and used with many types of microchips, integrated circuits and other microelectronic devices. Generally speaking, “DFT” describes any number of design techniques that allow for the testing of hardware that has been designed or manufactured. Often, DFT structures are implemented within microelectronic products to validate that the product contains no manufacturing or design defects that might adversely affect performance. Test data, for example, is often applied to the manufactured component under test (often using a “scan chain” or series of dedicated registers), and test results are obtained by letting the component process the applied data. If the resulting output matches an expected value, then the component under test can be considered to be functioning normally.
Recent developments in hardware design, however, have made DFT testing even more complicated. Although DFT techniques have long been applied to chips or other circuits that operate in response to a single clock signal, for example, DFT is much more complicated when testing data paths that span multiple chips or other components that are separately clocked. Multi-chip modules (MCMs), for example, can transmit data across multiple dies, chips or other components that each have their own clock signals, thereby making control of the entire data path difficult. Other types of systems (including data processing systems implemented on a common chip, package, circuit board or the like) can experience similar issues.
Although some attempts have been made to apply a test capture clock signal across multiple clock domains, these attempts generally have not been as successful as desired. In particular, prior attempts to use DFT techniques with a common capture clock signal applied to multiple chips or other clock domains have typically resulted in “hold time” errors wherein the time for the input data to propagate through the multi-domain path exceeds the time available to capture the data. It can therefore be relatively challenging to provide effective DFT testing across multiple clock domains.